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asahi kasei [AK4124] ms0288-e-01 2004/08 - 1 - general description AK4124 is a stereo digital sample rate converter (s rc). the input sample rate ranges from 8khz to 216khz. the output sample rate is from 8khz to 216khz. by using the AK4124, the system can take very simple configuration because the AK4124 has an internal pll and does not need any master clock at slave mode. then the AK4124 is suitable for the application interfacing to different sample rates like high-end car audio, dvd recorder, etc. features 1. src ? asynchronous sample rate converter ? input sample rate range (fsi) : 8khz 216khz ? output sample rate (fso) : 8khz 216khz ? input to output sample rate ratio : 1/6 to 6 ? thd+n : ? 130db ? dynamic range : 140db (a-weighted) ? i/f format : msb justified, lsb justified and i 2 s compatible ? pll for internal operation clock ? clock for master mode : 128/192/256/ 384/512/768fsi, 128/ 192/256/384/512/768fso ? src bypass mode ? soft mute function 2. power supply ? avdd, dvdd: 3.0 3.6v (typ. 3.3v) 3. ta = ? 40 85 c 4. package : 30pin vsop pll pdn smute olrck obick sdto omclk serial audio i/f src serial audio i/f ilrck sdti ibick pll1 pll2 idif2 idif1 idif0 odif1 odif0 obit1 obit0 unlock imclk avdd avss dvdd dvss cmode2 cmode1 cmode0 pll0 dither 192khz / 24bit high perfor mance asynchronous src AK4124
asahi kasei [AK4124] ms0288-e-01 2004/08 - 2 - ? ordering guide AK4124vf ? 40 +85 c 30pin vsop (0.65mm pitch) akd4124 evaluation board for AK4124 ? pin layout pdn smute ilrck ibick filt avss dither pll2 idif0 idif1 idif2 pll0 pll1 sdti top view 8 7 6 5 4 3 2 1 23 24 25 26 27 28 29 30 dvdd omclk sdto obick olrck dvss avdd 9 10 11 12 13 14 20 21 22 cmode2 17 18 19 obit1 imclk cmode0 odif0 odif1 cmode1 16 obit0 unlock 15
asahi kasei [AK4124] ms0288-e-01 2004/08 - 3 - ? compatibility with ak4121 AK4124 ak4121 pin 5 dither dem0 pin 6 pll2 dem1 thd+n ? 130db ? 113db d-range (a-weighted) 140db 117db gain between input and output signal ? 0.01db (typ) ? 0.2db (typ) fs 8khz 216khz 8khz 96khz master mode for input port yes no mclk for master mode (input port) 128/192/256/384/512/768fsi no mclk for master mode (output port) 128/192/256/384/512/768fso 256/384/512/768fso output data length 16/18/20/24 bit 16/20 bit de-emphasis filter no yes (32k/44.1k/48khz) pll unlock flag (unlock pin) yes no 5v tolerant no yes (tvdd) package 30vsop 24vsop
asahi kasei [AK4124] ms0288-e-01 2004/08 - 4 - pin/function no. pin name i/o function 1 filt o pll loop filter pin 2 avss - analog ground pin 3 pdn i power-down mode pin ?h?: power up, ?l?: power down reset and initializes the control register. 4 smute i soft mute pin ?h? : soft mute, ?l? : normal operation 5 dither i dither enable pin ?h? : dither on, ?l? : dither off 6 pll2 i pll mode select 2 pin 7 ilrck i/o input channel clock pin 8 ibick i/o audio serial data clock pin 9 sdti i audio serial data input pin 10 idif0 i audio interface format 0 pin for input port 11 idif1 i audio interface format 1 pin for input port 12 idif2 i audio interface format 2 pin for input port 13 pll0 i pll mode select 0 pin 14 pll1 i pll mode select 1 pin 15 unlock o unlock status pin 16 obit0 i bit length select 0 pin for output data 17 obit1 i bit length select 1 pin for output data 18 imclk i master clock input pin for input port 19 cmode0 i clock mode select 0 pin 20 cmode1 i clock mode select 1 pin 21 cmode2 i clock mode select 2 pin 22 odif0 i audio interface format 0 pin for output port 23 odif1 i audio interface format 1 pin for output port 24 sdto o audio serial data output pin for output port 25 obick i/o audio serial data clock pin for output port 26 olrck i/o output channel clock pin for output port 27 omclk i master clock input pin for output port 28 dvdd - digital power supply pin, 3.0 3.6v 29 dvss - digital ground pin 30 avdd - analog power supply pin, 3.0 3.6v note: all input pins should not be left floating.
asahi kasei [AK4124] ms0288-e-01 2004/08 - 5 - ? handling of unused pins the unused digital i/o pins should be processed appropriately as below. classification pin name setting analog filt this pin should be open. digital smute, dither these pins should be connected to dvss. imclk, omclk these pins should be connected to dvss in slave mode. unlock this pin should be open. absolute maximum ratings (avss, dvss=0v; note 1) parameter symbol min max units power supplies: analog digital |avss ? dvss| (note 2) avdd dvdd ? gnd ? 0.3 ? 0.3 - 4.6 4.6 0.3 v v v input current, any pin except supplies iin - 10 ma digital input voltage vind ? 0.3 dvdd+0.3 v ambient temperature (power applied) ta ? 40 85 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. avss, bvss and dvss must be connected to the same ground. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v; note 1) parameter symbol min typ max units power supplies (note 3) analog digital avdd dvdd 3.0 3.0 3.3 3.3 3.6 avdd v v note 1. all voltages with respect to ground. note 3. the power up sequence between avdd and dvdd is not critical. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
asahi kasei [AK4124] ms0288-e-01 2004/08 - 6 - src characteristics (ta=25 c; avdd=dvdd=3.3v; avss=dvss=0v; data = 24bit; measurement bandwidth = 20hz ~ fso/2; unless otherwise specified.) parameter symbol min typ max units src characteristics: resolution 24 bits input sample rate fsi 8 216 khz output sample rate fso 8 216 khz thd+n (input = 1khz, 0dbfs, note 4) fso/fsi = 44.1khz/48khz fso/fsi = 48khz/44.1khz fso/fsi = 48khz/192khz fso/fsi = 192khz/48khz worst case (fso/fsi = 48khz/8khz) - - - - - ? 130 ? 124 ? 129 ? 124 - - - - - ? 108 db db db db db dynamic range (input = 1khz, ? 60dbfs, note 4) fso/fsi = 44.1khz/48khz fso/fsi = 48khz/44.1khz fso/fsi = 48khz/192khz fso/fsi = 192khz/48khz worst case (fso/fsi = 48khz/32khz) dynamic range (input = 1khz, ? 60dbfs, a-weighted, note 4) fso/fsi = 44.1khz/48khz - - - - 132 - 136 136 136 132 - 140 - - - - - - db db db db db db ratio between input and output sample rate fso/fsi 1/6 6 - note 4. measured by audio precision system two cascade.
asahi kasei [AK4124] ms0288-e-01 2004/08 - 7 - filter characteristics (ta=25 c; avdd, dvdd=3.0 3.6v) parameter symbol min typ max units digital filter 0.985 fso/fsi 6.000 pb 0 0.4583fsi khz 0.905 fso/fsi < 0.985 pb 0 0.4167fsi khz 0.714 fso/fsi < 0.905 pb 0 0.3195fsi khz 0.656 fso/fsi < 0.714 pb 0 0.2852fsi khz 0.536 fso/fsi < 0.656 pb 0 0.2182fsi khz 0.492 fso/fsi < 0.536 pb 0 0.1982fsi khz 0.452 fso/fsi < 0.492 pb 0 0.1740fsi khz 0.357 fso/fsi < 0.452 pb 0 0.1212fsi khz 0.324 fso/fsi < 0.357 pb 0 0.1072fsi khz 0.246 fso/fsi < 0.324 pb 0 0.0595fsi khz 0.226 fso/fsi < 0.246 pb 0 0.0484fsi khz passband ? 0.001db 0.1667 fso/fsi < 0.226 pb 0 0.0182fsi khz 0.985 fso/fsi 6.000 sb 0.5417fsi khz 0.905 fso/fsi < 0.985 sb 0.5021fsi khz 0.714 fso/fsi < 0.905 sb 0.3965fsi khz 0.656 fso/fsi < 0.714 sb 0.3643fsi khz 0.536 fso/fsi < 0.656 sb 0.2974fsi khz 0.492 fso/fsi < 0.536 sb 0.2732fsi khz 0.452 fso/fsi < 0.492 sb 0.2510fsi khz 0.357 fso/fsi < 0.452 sb 0.1983fsi khz 0.324 fso/fsi < 0.357 sb 0.1822fsi khz 0.246 fso/fsi < 0.324 sb 0.1366fsi khz 0.226 fso/fsi < 0.246 sb 0.1255fsi khz stopband 0.1667 fso/fsi < 0.226 sb 0.0911fsi khz passband ripple pr 0.01 db stopband attenuation sa 113 db group delay (note 5) gd - 56 - 1/fs note 5. this value is the time from the rising edge of lrck after data is input to rising edge of lrck after data is output, when lrck for output data corresponds with lrck for input. dc characteristics (ta=25 c; avdd, dvdd=3.0 3.6v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%dvdd - - - - 30%dvdd v v high-level output voltage (iout= ? 400 a) low-level output voltage (iout=400 a) voh vol dvdd ? 0.4 - - - - 0.4 v v input leakage current iin - - 10 a power supplies power supply current normal operation (pdn pin = ?h?) fsi=fso=48khz at slave mode: avdd=dvdd=3.3v fsi=fso=192khz at master mode: avdd=dvdd=3.3v : avdd=dvdd=3.6v power down (pdn pin = ?l?) (note 6) avdd+dvdd 13 55 10 85 100 ma ma ma a note 6. all digital input pins are held dvss.
asahi kasei [AK4124] ms0288-e-01 2004/08 - 8 - switching characteristics (ta=25 c; avdd, dvdd=3.0 3.6v; c l =20pf) parameter symbol min typ max units master clock timing frequency pulse width low pulse width high fclk tclkl tclkh 1.024 0.4/fclk 0.4/fclk 41.472 mhz ns ns lrck for input data (ilrck) frequency duty cycle fs duty 8 48 50 216 52 khz % lrck for output data (olrck) frequency duty cycle slave mode master mode fs duty duty 8 48 50 50 216 52 khz % % audio interface timing input port (slave mode) ibick period (8khz 108khz) (108khz 216khz) ibick pulse width low pulse width high ilrck edge to ibick ? ? (note 7) ibick ? ? to ilrck edge (note 7) sdti hold time from ibick ? ? sdti setup time to ibick ? ? tbck tbck tbckl tbckh tlrb tblr tsdh tsds 1/128fs 1/64fs 27 27 15 15 15 15 ns ns ns ns ns ns ns ns input port (master mode) ibick frequency ibick duty ibick ? ? to ilrck sdti hold time from ibick ? ? sdti setup time to ibick ? ? fbck dbck tmblr tsdh tsds ? 20 15 15 64fs 50 20 hz % ns ns ns output port (slave mode) obick period (8khz 108khz) (108khz 216khz) obick pulse width low pulse width high olrck edge to obick ? ? (note 7) obick ? ? to olrck edge (note 7) olrck to sdto (msb) (except i 2 s mode) obick ? ? to sdto tbck tbck tbckl tbckh tlrb tblr tlrs tbsd 1/128fs 1/64fs 27 27 20 20 20 20 ns ns ns ns ns ns ns ns output port (master mode) obick frequency obick duty obick ? ? to olrck obick ? ? to sdto fbck dbck tmblr tbsd ? 20 ? 20 64fs 50 20 20 hz % ns ns reset timing pdn pulse width (note 8) tpd 150 ns note 7. bick rising edge must not occur at the same time as lrck edge. note 8. the AK4124 can be reset by bringing the pdn pin = ?l?.
asahi kasei [AK4124] ms0288-e-01 2004/08 - 9 - ? timing diagram 1/fclk mclk tclkh tclkl vih vil 1/fs lrck vih vil tbck bick tbckh tbckl vih vil clock timing lrck vih vil tblr bick vih vil tlrs sdto 50%dvdd tlrb tbsd tsds sdti vil tsdh vih audio interface timing (slave mode) note : bick shows ibick and obick, lrck shows ilrck and olrck.
asahi kasei [AK4124] ms0288-e-01 2004/08 - 10 - lrck bick 50%dvdd sdto 50%dvdd tbsd tsds sdti vil tsdh vih tmblr dbck 50%dvdd audio interface timing (master mode) note : bick shows ibick and obick, lrck shows ilrck and olrck. tpd pdn vil power down & reset timing
asahi kasei [AK4124] ms0288-e-01 2004/08 - 11 - operation overview ? system clock & audio interface format for input port the input port works in master mode or slave mode. an internal system clock is created by the internal pll using ilrck (mode 0 2 of table 2) or ibick (mode 4 7 of table 2) in slave mode. the mclk is not needed in slave mode. and an internal system clock is created by imclk (mode 8 15 of table 2) in master mode. the pll2-0 pins and idif2-0 pins select the master/slave and pll mode. the pll2-0 pins and idif2-0 pins should be controlled when pdn pin = ?l?. the idif2-0 pins select the audio interface format for the input port. the audio data is msb first, 2?s compliment format. the sdti is latched on the rising edge of ibick. select the audio interface format when pdn pin = ?l?. when in bypass mode, both ibick and obick are fixed to 64fs. mode idif2 idif1 idif0 sdti format ilrck ibick ibick freq master / slave 0 l l l 16bit, lsb justified 32fsi 1 l l h 20bit, lsb justified 40fsi 2 l h l 24/20bit, msb justified 48fsi 3 l h h 24/16bit, i 2 s compatible 48fsi or 32fsi 4 h l l 24bit, lsb justified input input 48fsi slave 5 h l h 24bit, msb justified 64fs 6 h h l 24bit, i 2 s compatible output output 64fs master 7 h h h reserved table 1. input audio interface format (input port) mode master / slave p ll2 pll1 pll0 ilrck freq ibick freq imclk smute (note 5) 0 l l l 8k 96khz 1 l l h manual 2 l h l 8k 216khz 16k 216khz (note 1) depending on idif2-0 not needed. (note 4) semi-auto 3 l h h reserved 4 h l l 32fsi (note 3) 5 h l h 64fsi 6 h h l 128fsi manual 7 slave imclk = dvss ibick = input ilrck = input h h h 8k 216khz (note 2) 64fsi not needed. (note 4) semi-auto 8 l l l 8k 216khz 128fs 9 l l h 8k 108khz 256fs 10 l h l 8k 54khz 512fs manual 11 l h h 8k 216khz 128fs semi-auto 12 h l l 8k 216khz 192fs 13 h l h 8k 108khz 384fs 14 h h l 8k 54khz 768fs manual 15 master imclk = input ibick = output ilrck = output h h h 8k 216khz 64fs 192fs semi-auto table 2. pll setting (input port) note 1. pll lock rage is changed by the value of r and c connected filt pin. refer to ?pll loop filter?. note 2. the ibcik must be continuous except when the clocks are changed. note 3. ibcik = 32fsi is supported only 16bit lsb justified and i 2 s compatible. note 4. fixed to dvss. note 5. refer to ?soft mute operation? for manual mode and semi-auto mode.
asahi kasei [AK4124] ms0288-e-01 2004/08 - 12 - ilrck ibick(32fs) 0 110 2 3 9 1112131415 0 12 3 1 0 10 9 1112131415 sdti(i) don't care 1 0 15 14 13 210 15 14 13 12 12 don't care 15:msb, 0:lsb sdti(i) 15 14 13 76543 210 15 14 13 15 76543 210 ibick(64fs) 0 118 2 3 19 20 31 0 1 2 3 1 0 18 19 20 31 17 17 lch data rch data figure 1. mode 0 timing ilrck ibick(64fs) 0 1 224310 12 1 0 31 24 sdti(i) don't care 0 8 10 19:msb, 0:lsb lch data rch data 19 8 don't care 19 1 12 13 13 12 figure 2. mode 1 timing ilrck ibick(64fs) 0 1 2202124310 12 1 0 22 20 21 31 24 22 23 23 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data don't care 4321 23 22 23 22 23 1 2 3 4 figure 3. mode 2,5 timing (24bit msb) ilrck ibick(64fs) 0 1 225 21 24 0 12 1 0 22 25 21 24 22 23 23 3 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data don't care 4321 23 22 23 22 1 2 3 4 figure 4. mode 3, 6 timing (24bit i 2 s)
asahi kasei [AK4124] ms0288-e-01 2004/08 - 13 - ilrck ibick(64fs) 0 1 224310 12 1 0 31 24 89 89 sdti(i) don't care 0 8 10 23:msb, 0:lsb lch data rch data 23 8 don't care 23 1 figure 5. mode 4 timing ? system clock & audio interface format for output port the output port works in master mode or slave mode. the mclk is not needed in slave mode. the cmode2-0 pins select the master/slave and bypass mode. the cmode2-0 pins should be controlled when pdn pin = ?l?. the odif1-0 pins and obit1-0 pins select the audio interface format for the output port. the audio data is msb first, 2?s compliment format. the sdto is clocked out on the falling edge of obick. select the audio interface format when pdn pin = ?l?. when in bypass mode, both ibick and obick are fixed to 64fs. mode cmode 2 cmode 1 cmode0 master / slave omclk fso 0 l l l master 256fso 8k 108khz 1 l l h master 384fso 8k 108khz 2 l h l master 512fso 8k 54khz 3 l h h master 768fso 8k 54khz 4 h l l slave not used. set to dvss. 8k 216khz 5 h l h master 128fso 8k 216khz 6 h h l master 192fso 8k 216khz 7 h h h master (bypass) not used. set to dvss. 8k 216khz table 3. master/slave control (output port) mode odif1 odif0 sdto format 0 l l lsb justified 1 l h (reserved) 2 h l msb justified 3 h h i 2 s compatible table 4. output audio interface format 1 (output port) obick frequency mode master / slave obit1 obit0 sdto olrck obick msb justified, i 2 s lsb justified 0 l l 16bit 32fso 1 l h 18bit 36fso 2 h l 20bit 40fso 3 slave cmode2-0 = ?hll? h h 24bit input input 48fso 64fso 4 l l 16bit 5 l h 18bit 6 h l 20bit 7 master except cmode2-0 = ?hll? h h 24bit output output 64fso table 5. output audio interface format 2 (output port)
asahi kasei [AK4124] ms0288-e-01 2004/08 - 14 - olrck obick(64fs) 0 1 lch data rch data 89 sdto(o) 15:msb, 0:lsb sdto(o) 17:msb, 0:lsb sdto(o) 19:msb, 0:lsb sdto(o) 23:msb, 0:lsb 1 0 12 13 14 11 10 16 17 15 20 21 22 29 23 31 30 10 9 8 11 15 14 2 1 0 10 9 8 11 15 14 2 1 0 17 16 10 9 8 11 15 14 2 1 0 17 16 19 18 10 9 8 11 15 14 2 1 0 17 16 19 18 21 20 23 22 12 13 14 11 8 9 10 16 17 15 20 21 22 29 23 31 30 0 1 2 10 9 2 11 15 14 0 1 8 2 8 15 14 11 0 1 17 16 10 9 2 8 15 14 9 0 1 17 16 19 18 11 10 2 8 15 11 10 9 0 1 17 16 19 18 21 20 23 22 14 figure 6. lsb timing olrck obick(64fs) 0 1 2 lch data rch data 34 sdto(o) sdto(o) sdto(o) sdto(o) 23:msb, 0:lsb 34 15:msb, 0:lsb 17:msb, 0:lsb 19:msb, 0:lsb 321 4 8765 0 10 9 21 20 23 22 321 4 65 0 17 16 19 18 321 4 15 14 0 17 16 15 14 13 12 2 1 0 321 4 8765 0 10 9 21 20 23 22 321 4 65 0 17 16 19 18 321 4 15 14 0 17 16 15 14 13 12 2 1 0 0 31 1 2 0 31 1 2 19 18 17 24 13 14 16 15 20 21 23 22 19 18 17 24 13 14 16 15 20 21 23 22 23 22 19 18 17 16 15 14 figure 7. msb timing olrck obick(64fs) 0 1 2 lch data rch data 34 sdto(o) sdto(o) sdto(o) sdto(o) 23:msb, 0:lsb 34 15:msb, 0:lsb 17:msb, 0:lsb 19:msb, 0:lsb 012 0 31 1 2 19 18 17 24 14 16 15 20 21 23 22 19 18 17 24 14 16 15 20 21 23 22 23 19 17 15 15 14 13 12 2 1 0 321 4 15 14 0 17 16 321 4 65 0 17 16 19 18 321 4 8765 0 10 9 21 20 23 22 15 14 13 12 2 1 0 321 4 15 14 0 17 16 321 4 65 0 17 16 19 18 321 4 8765 0 10 9 21 20 23 22 figure 8. i 2 s compatible timing
asahi kasei [AK4124] ms0288-e-01 2004/08 - 15 - ? soft mute operation 1. manual mode soft mute operation is performed in the digital domain of the src output. soft mute can be controlled by smute pin. when smute pin goes ?h?, the src output data is attenuated by ? within 1024 olrck cycles. when the smute pin goes ?l? the mute is cancelled and the output attenuation gradually changes to 0db during 1024 olrck cycles. if the soft mute is cancelled before mute state after starting of the operation, the attenuation is discontinued and returned to 0db by the same cycles. the soft mute is effective for changing the signal source. smute a ttenuation 0db - gd gd (1) (2) (3) sdto 1024/fso figure 9. soft mute function (manual mode) (1) the output data is attenuated by ? during 1024 olrck cycles (1024/fso). (2) digital output delay from the digital input is called the group delay (gd). (3) if the soft mute is cancelled before attenuating to ? after starting the operation, the attenuation is discontinued and returned to 0db by the same number of clock cycles. 2. semi-auto mode the soft mute is cancelled automatically by the setting of pll2-0 pins (refer to table 2), after the AK4124 detects the rising edge (pdn pin = ?l? ?h?) and the mute is continued duri ng 4410/fso=100ms@fso=44.1khz. after pdn pin = ?l? ?h? and when smute pin is ?h?, the mute is not cancelled. pdn pin a ttenuation 0db - sdto gd 4410/fso (1) (2) smute pin don?t care ?l? ?l? figure 10. soft mute function (semi-auto mode) (1) the output data is attenuated by ? during 1024 olrck cycles (1024/fso). (2) digital output delay from the digital input is called the group delay (gd).
asahi kasei [AK4124] ms0288-e-01 2004/08 - 16 - ? dither the AK4124 has the dither circuit. the dither circuit adds the dither to the lsb of the output data set with the obit1-0 pins by dither pin = ?h" regardless of the src mode or the src bypass mode. ? system reset bringing the pdn pin = ?l? sets the AK4124 power-down mode and initializes the digital filter. the AK4124 should be reset once by bringing pdn pin = ?l? upon power-up. when pdn pin = ?l?, the sdto output is ?l?. the sdto valid time is 100ms. until then, the sdto outputs ?l?. case 1 external clocks (input port) sdti don?t care sdto (internal state) power-down normal operation pll lock & fs detection < 100ms normal data input clocks 1 external clocks (output port) don?t care don?t care pdn power-down don?t care don?t care don?t care ?0? data normal operation pll lock & fs detection < 100ms normal data pd input data 1 output clocks 1 input clocks 2 input data 2 output clocks 2 ?0? data ?0? data unlock figure 11. system reset case 2 external clocks (input port) sdti sdto (internal state) power-down normal operation pll lock & fs detection < 100ms normal data (no clock) external clocks (output port) pdn power-down don?t care don?t care don?t care ?0? data pll unlock input clocks input data output clocks ?0? data (don?t care) (don?t care) unlock figure 12. system reset 2
asahi kasei [AK4124] ms0288-e-01 2004/08 - 17 - ? internal reset function for clock change the change of the clock supplied to AK4124 is shown in figure 13. when the frequency transition occurs gradually without phase change or the clock of output port is changed keeping fso/fsi > 4, the internal reset is not executed and the sdto takes time over 100ms to output normal data. to output normal data within 100ms, please reset by pdn pin = ?l?. pll lock & fs detection power-down external clocks (input port or output port) clocks 1 sdto (internal state) normal operation normal operation clocks 2 don?t care < 100ms smute (note2, recommended) 1024/fso a tt.level 0db - db normal data normal data 1024/fso pdn pin note1 figure 13. sequence of changing clocks note 1. the data on sdto may cause a clicking noise. to prevent this, set sdti to ?0? from gd before pdn pin goes ?l?, which will cause the data on sdto to remain ?0?. note 2. smute can also be used to remove the unknown data. ? unlock pin the unlock pin outputs ?l? when the internal pll is locked. when the internal pll is unlocked, the unlock pin outputs ?h?. when pdn pin = ?l?, the unlock pin outputs ?h?.
asahi kasei [AK4124] ms0288-e-01 2004/08 - 18 - ? pll loop filter the c1 and r should be connected in series and attached between filt pin and avss in parallel with c2. please be careful the noise onto the filt pin. when using ibick, the value of an external element doesn't depend on the ibick input frequency. AK4124 c1 r filt a vss c2 figure 14. pll loop filter [input port in slave mode] 1. when using ilrck pll2 pll1 pll0 ilrck r [ ? ] c1 [ f] c2 [nf] l l l 8k 96khz 1.8k 5% 0.68 30% 0.68 30% 8k 216khz 1k 5% 1.0 30% 2.2 30% l l h 16k 216khz 1.5k 5% 0.68 30% 0.68 30% 8k 216khz 1k 5% 1.0 30% 2.2 30% l h l 16k 216khz 1.5k 5% 0.68 30% 0.68 30% table 6. pll loop filter (ilrck mode) - note. the mode of between 16khz and 216khz the capacitor value (c1, c2) can be small. 2. when using ibick pll2 pll1 pll0 ilrck r [ ? ] c1 [ f] c2 [nf] h * * 8k 216khz 470 5% 0.22 30% 1.0 30% table 7. pll loop filter (ibick mode, *: don?t care) note. the ibcik must be continuous except when the clocks are changed. note. ibcik = 32fsi is supported only 16bit lsb justified and i 2 s compatible. [input port in master mode] 1. when imclk is 256fs, 384fs, 512fs or 768fs, an external element is not needed. 2. when imclk is 128fs or 192fs in master mode, an external element is needed in case of using ibick.
asahi kasei [AK4124] ms0288-e-01 2004/08 - 19 - system design figure 15 shows the system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. ? input port : slave mode, ibick lock mode (64fsi), 24bit msb justified ? output port : slave mode, 24bit msb justified ? dither = off filt 1 3 4 5 6 7 8 9 10 11 avss pdn smute dither pll2 ilrck ibick sdti idif0 idif1 AK4124 30 29 28 avdd dvss dvdd 12 idif2 13 pll0 14 pll1 27 26 omclk olrck 25 24 obick sdto odif1 odif0 21 20 cmode2 cmode1 19 18 cmode0 imclk 17 obit1 22 23 15 unlock 16 obit0 1.0n 2 10 0.1 0.1 supply 3.0 ~ 3.6v 470 fsi 64fsi 64fso fso reset dsp dsp, up 0.22 note: - avss and dvss of the AK4124 should be distributed separately from the ground of external digital devices (mpu, dsp etc.). - all digital input pins should not be left floating. figure 15. typical connection diagram (slave mode)
asahi kasei [AK4124] ms0288-e-01 2004/08 - 20 - ? input port : slave mode, ibick lock mode (64fsi), 24bit msb justified ? output port : master mode, 24bit msb justified ? dither = off filt 1 3 4 5 6 7 8 9 10 11 avss pdn smute dither pll2 ilrck ibick sdti idif0 idif1 AK4124 30 29 28 avdd dvss dvdd 12 idif2 13 pll0 14 pll1 27 26 omclk olrck 25 24 obick sdto odif1 odif0 21 20 cmode2 cmode1 19 18 cmode0 imclk 17 obit1 22 23 dsp 15 unlock 16 obit0 1.0n 2 dsp, up 10 0.1 supply 3.0 ~ 3.6v 470 fsi 64fsi 64fso fso 128fso reset 0.1 0.22 note: - avss and dvss of the AK4124 should be distributed separately from the ground of external digital devices (mpu, dsp etc.). - all digital input pins should not be left floating. figure 16. typical connection diagram (master mode) 1. grounding and power supply decoupling the AK4124 requires careful attention to power supply and grounding arrangements. alternatively if avdd and dvdd are supplied separately, the power up sequence is not critical . decoupling capacitors should be as near to the AK4124 as possible, with the small value ceramic capacitor being the nearest.
asahi kasei [AK4124] ms0288-e-01 2004/08 - 21 - 2. jitter tolerance figure 17 shows the jitter tolerance to ilrck and ibick for AK4124. the jitter frequency and the jitter amplitude shown in figure 17 define the jitter quantity. when the jitter amplitude is 0.01uipp or less, the AK4124 operate normally regardless of the jitter frequency. (1) normal operation (2) there is a possibility that the distortion degrades. (it may degrade up to about ? 50db.) (3) there is a possibility that the output data is lost. note: - when pll2-0 = ?l/l/l?, ?l/l/h?, ?l/h/l?, the jitter amplitude is for ilrck and 1ui (unit interval) is one cycle of ilrck. when fsi = 48khz, 1ui is 1/48khz = 20.8 s. - when pll2-0 = ?h/*/*? (*: don?t care), the jitter amplitude is for ibick and 1ui (unit interval) is one cycle of ibick. when fsi = 48khz, 1ui is 1/(64 x 48khz) = 326ns. figure 17. jitter tolerance AK4124 jitter tolerance 0.00 0.01 0.10 1.00 10.00 1 10 100 1000 10000 jitter frequency [hz] amplitude [uipp] (3) (2) (1)
asahi kasei [AK4124] ms0288-e-01 2004/08 - 22 - package detail a note: dimension "*" does not include mold flash. 0.22 0.1 0.65 *9.7 0.1 1.5max a 1 15 16 30 30pin vsop (unit: mm) 5.6 0.1 7.6 0.2 0.45 0.2 -0.05 +0.10 0.3 0.15 0.12 m 0.08 1.2 0.10 0.10 +0.10 -0.05 ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
asahi kasei [AK4124] ms0288-e-01 2004/08 - 23 - marking akm a k4124vf xxxbyyyyc xxxbyyyyc date code identifier xxxb : lot number (x : digit number, b : alpha character) yyyyc : assembly date (y : digit number, c : alpha character) revision history date (yy/mm/dd) revision reason page contents 04/01/26 00 first edition add spec 7 add filter characteristics 04/08/09 01 add spec 21 add jitter tolerance
asahi kasei [AK4124] ms0288-e-01 2004/08 - 24 - important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsyst ems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: a. a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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